The present invention relates to a semiconductor integrated circuit having both an operation mode large in power consumption and a standby mode small in power consumption, and more particularly to a semiconductor integrated circuit reduced in power consumption when it operates at a low voltage.
With the spread of portable devices and in view of energy saving, a reduction in power consumption is recently demanded for a semiconductor integrated circuit (hereinafter referred to as LSI). To reduce an LSI in power consumption, it is effective to lower the power supply voltage. Further, to assure the reliability of a transistor of which miniaturization is progressed, a reduction in power supply voltage becomes an essential condition in LSI designing. Conventionally, the inside power supply of an LSI is mainly set to 3 to 5 V, but an LSI operable at 0.8 V.about.1.5 V is now desired for a battery-driven LSI. On the other hand, each of the MOS transistors forming an LSI has a threshold voltage. When the power supply voltage is lowered and approaches the predetermined threshold voltage of each transistor, the drive ability of each transistor is lowered to lower the drive current thereof. This lowers the LSI in performance. In this connection, to provide a predetermined performance even at a low voltage, there are used low-threshold transistors higher in drive current. However, low-threshold transistors are high in drive current at a low voltage and also high in off-leak current in the standby mode. This increases the current in the standby mode to increase the power consumption, resulting in a failure to achieve the original object of a reduction in power consumption. In this connection, there have been proposed MTCMOS transistors disclosed by Japanese Patent Laid-Open Publication No. 6-29834, in which high-threshold transistors are disposed between the power supply and a circuit formed by low-threshold transistors and in which the off-leak current is reduced in the standby mode by turning off these high-threshold transistors.
As another method of reducing the off-leak current, there is available a method disclosed by Japanese Patent Laid-Open Publication No. 6-208790, with the object of reducing the off-leak current in the standby mode.
However, any of the conventional semiconductor integrated circuits can reduce only the off-leak current in the standby mode and disadvantageously generates a feedthrough leak current together with charging and discharging currents in the operation mode. This is particularly remarkable in a circuit in which the operation period of time is long or which operates in a region relatively high in frequency, because the influence in the operation mode is greater.